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cy24c01/02/04/08/16 1 kbit, 2 kbit, 4 kbit, 8 kbit, and 16 kbit (x8) two wire (i2c) serial eeprom cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-15632 rev. *c revised february 05, 2009 features continuous voltage operation ? v cc = 1.65v to 5.5v internally organized as 128 x 8 (1k), 256 x 8 (2k), 512 x 8 (4k), 1024 x 8 (8k), or 2048 x 8 (16k) industry standard two wire serial interface schmitt trigger, filtered inputs for noise suppression bidirectional data transfer protocol 1 mhz (2.5v - 5.5v), 400 khz (1.65v - 5.5v), and 100 khz (1.65v - 5.5v) compatibility write protect pin for hardware data protection 16-byte page write mode partial page writes enabled self timed write cycle (5 ms max) high reliability ? endurance: 1 million write cycles ? data retention: 100 years industrial temperature range 8-pin soic and 8-pin tssop packages pb-free and rohs compliant functional description the cy24c01/02/04/08/16 range of products provide 1k, 2k, 4k, 8k, and 16k bits of serial electrically erasable and program- mable read only memory (eeprom) organized as 128, 256, 512, 1024, and 2048 words of eight bits each. the device is optimized for use in many industrial applications where low power and low voltage operations are essential. the cy24c01/02/04/08/16 is available in space saving 8-pin soic and 8-pin tssop packages and is accessed through a two-wire serial interface. in addition, the entire family is available in 1.65v (1.65v to 5.5v) version. logic block diagram scl sda a0?a2 wp cy24c01/02/04/08/16 v ss v cc [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 2 of 16 pinouts figure 1. pin diagram - 8-pin soic/tssop package table 1. pin definitions - 8-pin soic/tssop package pin name 8-soic/tssop pin number i/o type description a0?a2 1,2,3 input device address pins. the cy24c01 and cy24c02 uses the a2, a1, and a0 inputs for hard wire addressing and a total of eight 1k and 2k devices may be addressed on a single bus system. the cy24c04 uses the a2 and a1 inputs for hard wire addressing and a total of four 4k devices may be addressed on a single bus system. the a0 pin is a no connect. the cy24c08 uses only the a2 input for hardwire addressing and a total of two 8k devices may be addressed on a single bus system. the a0 and a1 pins are no connects. the cy24c16 does not use the device addr ess pins which limit the number of devices on a single bus to one. the a0, a1, and a2 pins are no connects. v ss 4 ground ground. the ground for the device. it must be connected to the ground of the system. sda 5 input/output serial data. the sda pin is bidirectional for serial data transfer. this pin is open drain driven and is wired-ored with any number of other open drain or open collector devices. scl 6 input serial clock. the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. wp 7 input write protect. the cy24c01/02/04/08/16 has a wr ite protect pin that provides hardware data protection. th e write protect pin allo ws normal read and write operations when connected to ground (gnd). when the write protect pin is connected to vcc, the write protection feature is enabled and operates as shown in table 2 on page 3. v cc 8 power supply power supply. the power supply inputs to the device. a0 scl sda 1 2 3 4 5 6 7 8 top view (not to scale) a2 v cc v ss a1 wp [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 3 of 16 memory organization cy24c01 internally organized with eight pages of 16 bytes each, the 1k requires a 7-bit data word address for random word addressing. cy24c02 internally organized with 16 pages of 16-bytes each, the 2k requires a 8-bit data word address for random word addressing. cy24c04 internally organized with 32 pages of 16 bytes each, the 4k requires a 9-bit data word address for random word addressing. cy24c08 internally organized with 64 pages of 16 bytes each, the 8k requires a 10-bit data word address for random word addressing. cy24c16 internally organized with 128 pages of 16 bytes each, the 16k requires an 11-bit data word address for random word addressing. device operating features clock and data transitions the sda pin is normally pulled high with an external device. data on the sda pin changes only during scl low time periods. data changes during scl high periods indicate a start or stop condition as defined in the following section. start condition a high to low transition of sda with scl high is a start condition which must precede any other command (see figure 2 ). stop condition a low to high transition of sda with scl high is a stop condition. after a read sequence, the stop command places the eeprom in a standby power mode (see figure 2 ). acknowledge all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom acknowledges each word received by sending a zero during the ninth clock cycle. standby mode the cy24c01/02/04/08/16 features a low power standby mode, which is enabled on power up, after the receipt of the stop bit and the completion of any internal operations. device internal reset to prevent inadvertent write operations during power up, a power on reset (por) circuit is included. during power up (continuous rise of v cc ), the device does not respond to any instruction until the v cc reaches the por threshold voltage (this threshold is lower than the v cc minimum operating voltage defined in dc electrical characteristics on page 8). when v cc has passed over the por threshold, the device is reset and is in standby power mode. during power down (continuous decay of v cc ), when v cc drops from the normal operating voltage to below the por threshold voltage, the device stops responding to any instruction sent to it. be fore selecting and issuing instruc- tions to the memory, a valid and stable v cc voltage must be applied. this voltage must remain stable and valid until the end of the transmission of the instru ction and, for a write instruction, until the completion of th e internal write cycle (t wr ). memory reset after an interruption in protocol , power loss, or system reset, any two-wire part is reset with the following steps: 1. clock up to nine cycles. 2. look for sda high in ea ch cycle while scl is high. 3. create a start condition as sda is high. table 2. write protect wp pin status part of the memory protected cy24c01 cy24c02 cy24c04 cy24c08 cy24c16 v cc full 1k array full 2k array full 4k array full 8k array full 16k array v ss normal read/write operations figure 2. start/stop definition scl sda start bit stop bit [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 4 of 16 device addressing the cy24c01/02/04/08/16 eeprom requires an 8-bit device address word after a start condition, to enable the chip for a read or write operation (refer to table 3 on page 5). the device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown in table 3 on page 5. this is common to all the eeprom devices. the next three bits are the a2, a1, and a0 device address bits for cy24c01 and cy24c02. these three bits must compare to their corresponding hard wired input pins. cy24c04 uses only the a2 and a1 device address bits. the third bit is a memory page address bit. the two device address bits must compare to their corresponding hard wired input pins. the a0 pin is no connect. cy24c08 only uses the a2 device address bit with the next 2 bits being for memory page addressing. the a2 bit must compare to its corresponding hard wired input pin. the a1 and a0 pins are no connect. cy24c16 does not use any device address bits and the 3 bits are used for memory page addressing. the page addressing bits on the 4k, 8k, and 16k devices must be considered the most significant bits of the data word address which follows. the a0, a1, and a2 pins are no connect. the eighth bit of the device address is the read or write operation select bit. a read operation is init iated if this bit is high and a write operation is initiated if this bit is low. when the device address is compared, the eeprom outputs a zero. if a compare is not made, the chip returns to the standby state. write operations byte write a write operation requires an 8-bit data word address following the device address word and acknowledgment. on receipt of this address, the eeprom responds with a zero and then clocks in the first 8-bit data word. followin g the receipt of the 8-bit data word, the eeprom outputs a zero . the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this writ e cycle and the eeprom does not respond until the write is complete (see figure 4 on page 6). page write the cy24c01/02/04/08/16/cy 24c08/cy24c16 devices are capable of 16-byte page writes. a page write is initiated in the sa me way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, th e microcontroller can transmit up to 15 more data words. the eepr om responds with a zero after each data word is received. the microcontroller must terminate the page write sequence with a stop condition (see figure 5 on page 6). the lower four bits of the data word address are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the internally generated word address reaches the page boundary, the next byte is placed at the beginning of the same page. if more than 16 data words are transmitted to the eeprom, the data word address rolls over and the previous data is overwritten. acknowledge polling when the internally timed wr ite cycle has started and the eeprom inputs are disabled, acknowledge polling is initiated. this involves sending a start condition followed by the device address word. the read or write bit is representative of the operation desired. afte r the internal write cycle is complete, the eeprom responds with a zero, enabling the read or write sequence to continue. figure 3. acknowledge timing a a a a a a scl data in data out start acknowledge 1 8 9 [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 5 of 16 read operations read operations are initiated in the same way as write opera- tions except that the read or writ e select bit in the device address word is set to one. there ar e three read operations: current address read, random address read, and sequential read. current address read the internal data word address counter maintains the last address accessed during the last re ad or write operation, incre- mented by one. this address stays valid between operations as long as the chip power is maintained. the address roll over during read and byte write is from the last byte of the last memory page to the first byte of the first page. the address roll over during write is from the last byte of the current page to the first byte of the same page. after the device address with the read or write select bit set to one is clocked in and acknowledged by the eeprom, the current address data wo rd is serially clocked out. the microcontroller does not respond with an input zero but generates a stop condition (see figure 6 on page 6). random read a random read needs a ?dummy? byte write sequence to load in the data word address. after the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller mu st generate another start condition. the microcontroller in itiates a current address read by sending a device address with t he read or write select bit high. the eeprom acknowle dges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but generates a st op condition as shown in figure 7 on page 6. sequential read sequential reads are initiated by either a current address read or a random address read. after the mi crocontroller receives a data word, it responds with an acknowledgement. as long as the eeprom receives an acknowledgement, it continues to increment the data word addr ess and serially clocks out sequential data words. when the address memory limit is reached, the data word address rolls over and the sequential read continues. the sequential read operation is terminated when the microcontroller does not respond with a zero but generates a stop condition (see figure 8 on page 7). table 3. device addressing [1,2,3] density device type identifier chip enable address b7 b6 b5 b4 b3 b2 b1 b0 1k/2k 1 0 1 0 a2 a1 a0 r/w 4k 1 0 1 0 a2 a1 p0 r/w 8k 1 0 1 0 a2 p1 p0 r/w 16k 1 0 1 0 p2 p1 p0 r/w table 4. operating modes mode r/w bit wp bytes initial sequence current address read 1 x 1 start, device select, r/w = 1 random address read 0 x 1 start, device select, r/w = 0, address 1 x restart, devi ce select, r/w = 1 sequential read 1 x > 1 similar to current or random address read byte write 0 0 1 start, device select, r/w = 0 page write 0 0 < 16 start, device select, r/w = 0 notes 1. p2, p1, p0 are used for memory page addressing. 2. a2, a1 and a0 are compared against the resp ective external pins on the memory device. 3. the msb b7 is sent first. [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 6 of 16 figure 4. byte write timing [4] figure 5. page write timing figure 6. current address read timing figure 7. random address read timing s t o p t a r t a c k a c k a c k s p sda line slave address byte address data s t o p s t a r t a c k a c k a c k s p sda line slave address byte address (n) data n data n+1 data n+p a c k a c k s t o p s t a r t a c k n o a c k s p sda line slave address data note: 6 4. p 15 for cy24c04/08/16. s t o p s t a r t a c k n o a c k s sda line slave address byte address a c k s s t a r t slave address a c k data n p dmm wite note 4. p = 15 for cy24c04/08/16. [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 7 of 16 figure 8. sequential read timing s t o p a c k n o a c k p sda line slave address data n data n+1 data n+2 a c k a c k a c k data n+x a a [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 8 of 16 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .................................. ?65 c to +150 c ambient temperature with power applied ............................................. ?55 c to +125 c supply voltage on v cc relative to gnd..........?1.0v to +6.0v dc voltage applied to outputs in high-z state........................................ ?0.5v to v cc + 1.0v input voltage .......................................... ?0.5v to v cc + 0.5v transient voltage (<20 ns) on any pin to ground potential .................... ?1.0v to v cc + 2.0v package power dissipation capability (t a = 25c) .................................................... 1.0w surface mount lead soldering temperature (3 second s)................... +260 c for 10 seconds output short circuit current [5] ....................................... 50 ma static discharge voltage........................................... > 2001v (per mil-std-883, method 3015) latch up current .................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 c to +85 c 1.65v to 5.5v dc electrical characteristics over the operating range (vcc = 1.65v to 5.5v) parameter description test conditions min max unit v cc supply voltage 1.65 5.5 v i sb1 standby current v cc = 1.65v, v in = v ss or v cc 1 a i sb2 standby current v cc = 2.7v, v in = v ss or v cc 1.1 a i sb3 standby current v cc = 5.5v, v in = v ss or v cc 1.2 a i cc1 operating current (read) v cc = 5.5v at 1 mhz 2 ma i cc2 operating current (read) v cc = 5.5v at 400 khz 1 ma i cc3 operating current (write) v cc = 5.5v 2 ma i li input leakage current v in = v cc or v ss .1 a i lo output leakage current v out = v cc or v ss .1 a v il input low voltage v cc = v cc min ?0.6 [6] 0.3 v cc v v ih input high voltage v cc = v cc max 0.7 v cc v cc + 0.5 [6] v v ol output low voltage i ol = 3 ma, v cc = 5.5v 0.4 v i ol = 0.15 ma, v cc = 1.8v 0.2 note 5. outputs shorted for only one second. only one output shorted at a time. 6. this parameter is characterized but not tested. [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 9 of 16 capacitance in the following table, the capacitance parameters are listed. [7] parameter description test conditions max unit c in input capacitance (a0,a1, a2, scl) t a = 25 c, f = 1 mhz, v cc = 1.65v 6pf c io input/output capaci- tance (sda) 8pf thermal resistance in the following table, the thermal resistance parameters are listed. [7] parameter description test conditions 8-soic 8-tssop unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and proce- dures for measuring thermal impedance, per eia / jesd51. 120.83 119.31 c/w jc thermal resistance (junction to case) 90.31 82.77 c/w reliability characteristics in the following table, the reliability characteristics parameters are listed. [7] parameter description test method min unit n end endurance jedec standard a117 1 million cycles t dr data rentention jedec standard a103 100 years i lth latch up jedec standard 78 100 + i cc ma figure 9. ac test loads and waveforms frequency r (ohm) c l (pf) 1 mhz 1.2k 30 100 khz, 400 khz 2.7k 100 figure 10. ac input and output reference waveforms ac test inputs are driven at v iht (0.9 v cc ) for a logic ?1? and v ilt (0.1 v cc ) for a logic ?0?. measurement reference points for inputs and outputs are v lt (v cc /2 - 0.1v) and v ht (v cc /2 + 0.1v). input rise and fall times (10%?90%) are <100 ns. vcc output r c l v ht reference points input v iht v ilt output v lt v ht v lt note 7. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 10 of 16 ac switching ch aracteristics cypress parameter alt parameter description 1 mhz (2.5v - 5.5v) 400 khz (1.65v - 5.5v) 100 khz (1.65v - 5.5v) unit min max min max min max f scl f scl clock frequency, scl 1000 400 100 khz t cl t low clock pulse width low 0.4 0.6 4 s t ch t high clock pulse width high 0.4 0.6 4 s t aa t aa clock low to data out valid 0.4 0.9 4.5 s t i t i noise suppression time 25 50 50 ns t s.sta t su.sta start setup time 0.25 0.6 4 s t h.sta t hd.sta start hold time 0.25 0.6 4 s t sd t su.dat data in setup time 100 100 200 ns t hd t hd.dat data in hold time 0 0 0 s t doh t dh data out hold time 50 50 100 ns t s.sto t su.sto stop setup time 0.25 0.6 4 s t r t r inputs rise time 100 250 1000 ns t f t f inputs fall time 100 250 1000 ns t wc t wr write cycle time 5 5 5 ms t buf [6] t buf bus free time for new data transmission 0.5 1.3 4.7 s figure 11. bus timing t f t r t cl t ch t cl t sd t hd t s.sta t h.sta t s.sto t buf t aa t doh scl sda in sda out [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 11 of 16 figure 12. write timing part numbering nomenclature a a a a t wr scl sda stop condition start condition address 8th bit byte n ack cy24 c 01 - sx i t temperature: i = industrial (C40 to 85c) option: t=tape&reel blank = std. voltage: c = 1.65v - 5.5v cypress 24 = i2c interface package: s=soic z=tssop density: 16 = 16 kb 01 = 1 kb 02 = 2 kb 04 = 4 kb 08 = 8 kb x = pb-free [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 12 of 16 ordering information density ordering code package diagram package type operating range 1 kbit cy24c01-sxi 51-85066 8-pin soic industrial cy24c01-sxit 8-pin soic (tape & reel) cy24c01-zxi 51-85093 8-pin tssop cy24c01-zxit 8-pin tssop (tape & reel) 2 kbit cy24c02-sxi 51-85066 8-pin soic industrial cy24c02-sxit 8-pin soic (tape & reel) cy24c02-zxi 51-85093 8-pin tssop cy24c02-zxit 8-pin tssop (tape & reel) 4 kbit cy24c04-sxi 51-85066 8-pin soic industrial cy24c04-sxit 8-pin soic (tape & reel) cy24c04-zxi 51-85093 8-pin tssop cy24c04-zxit 8-pin tssop (tape & reel) 8 kbit cy24c08-sxi 51-85066 8-pin soic industrial CY24C08-SXIT 8-pin soic (tape & reel) cy24c08-zxi 51-85093 8-pin tssop cy24c08-zxit 8-pin tssop (tape & reel) 16 kbit cy24c16-sxi 51-85066 8-pin soic industrial cy24c16-sxit 8-pin soic (tape & reel) cy24c16-zxi 51-85093 8-pin tssop cy24c16-zxit 8-pin tssop (tape & reel) above table contains preliminary information. please contact your local cypress sales representative for availability of these parts. [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 13 of 16 package diagrams figure 13. 8-pin (150-mil) soic, 51-85066 seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 1 4 8 5 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 51-85066-*c [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 14 of 16 figure 14. 8-pin (4.4 mm) tssop, 51-85093 package diagrams (continued) 51-85093-*a [+] feedback
cy24c01/02/04/08/16 document #: 001-15632 rev. *c page 15 of 16 document history page document title: cy24c01/02/0 4/08/16, 1 kbit, 2 kbit, 4 kbit, 8 kbit, and 16 kbit (x8) two wi re (i2c) serial eeprom document number: 001-15632 revision ecn no. orig. of change submission date description of change ** 1069220 uha see ecn new data sheet *a 2522135 gvch/pyrs 06/27/08 added pb-free and ro hs compliant information in ?features? removed pdip package removed automotive temperature range updated figure 4. changed memory page addressing naming convention from a10,a9,a8 to p2,p1,p0 changed supply voltage on v cc relative to gnd max value from 5.0v to 6.0v corrected typo of vcc max value from 5.0v to 5.5v added i cc1 spec for 1 mhz table 8: added thermal resistance values for 8-tssop package added ac test load values for different frequency table 10: added tl (noise suppression time) value for 1 mhz and 100 khz frequency updated part numbering nomenclature and ordering information *b 2611873 vkn/pyrs 11/24/08 added 1 kbit and 2 kbit parts and their related information *c 2656511 vkn/pyrs 02/09/09 converted from preliminary to final changed v cc operating range for 1mhz operation from 1.65v-5.5v to 2.5v-5.5v changed i cc3 spec from 1.5ma to 2ma added footnote #6 updated v ol test conditions on page 9, corrected ac measurement reference points from v it and v ot to v lt and v ht respectively changed v lt level from 0.3v cc to v cc /2 - 0.1v changed v ht level from 0.7v cc to v cc /2 + 0.1v [+] feedback
document #: 001-15632 rev. *c re vised february 05, 2009 page 16 of 16 all products and company names mentioned in this document may be the trademarks of their respective holders. cy24c01/02/04/08/16 ? cypress semiconductor corporation, 2007-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb [+] feedback

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